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SN74LVC1G34 SINGLE BUFFER GATE
SCES519A - DECEMBER 2003 - REVISED JUNE 2004
D Available in the Texas Instruments D D D D D D D D
NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 3.5 ns at 3.3 V Low Power Consumption, 10-A Max ICC 24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101)
DBV OR DCK PACKAGE (TOP VIEW)
NC A GND
1 2 3
5 4
VCC Y
NC - No internal connection YEP OR YZP PACKAGE (BOTTOM VIEW)
GND A DNU
34 2 15
Y VCC
DNU - Do not use
description/ordering information
This single buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G34 performs the Boolean function Y = A in positive logic. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION
TA PACKAGE NanoStar - WCSP (DSBGA) 0.23-mm Large Bump - YEP NanoFree - WCSP (DSBGA) 0.23-mm Large Bump - YZP (Pb-free) -40 C to 85 C -40C 85C SOT (SOT-23) - DBV SOT (SC-70) - DCK Reel of 3000 SN74LVC1G34YZPR Reel of 3000 Reel of 250 Reel of 3000 Reel of 250 SN74LVC1G34DBVR SN74LVC1G34DBVT SN74LVC1G34DCKR SN74LVC1G34DCKT C9_ C34_ ORDERABLE PART NUMBER SN74LVC1G34YEPR _ _ _C9_ TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, * = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
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SN74LVC1G34 SINGLE BUFFER GATE
SCES519A - DECEMBER 2003 - REVISED JUNE 2004
FUNCTION TABLE INPUT A H L OUTPUT Y H L
logic diagram (positive logic)
A 2 4 Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
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SN74LVC1G34 SINGLE BUFFER GATE
SCES519A - DECEMBER 2003 - REVISED JUNE 2004
recommended operating conditions (see Note 4)
MIN Operating VCC Supply voltage Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 VCC = 1.65 V VCC = 2.3 V IOH High-level output current VCC = 3 V VCC = 4.5 V VCC = 1.65 V VCC = 2.3 V IOL Low-level output current VCC = 3 V VCC = 4.5 V VCC = 1.8 V 0.15 V, 2.5 V 0.2 V t/v Input transition rise or fall rate VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V 1.65 1.5 0.65 x VCC 1.7 2 0.7 x VCC 0.35 x VCC 0.7 0.8 0.3 x VCC 5.5 VCC -4 -8 -16 -24 -32 4 8 16 24 32 20 10 10 ns/V mA mA V V V V MAX 5.5 V UNIT
VIH
High-level input voltage
VIL
Low-level input voltage
VI VO
Input voltage Output voltage
TA Operating free-air temperature -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74LVC1G34 SINGLE BUFFER GATE
SCES519A - DECEMBER 2003 - REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 mA IOH = -4 mA VOH IOH = -8 mA IOH = -16 mA IOH = -24 mA IOH = -32 mA IOL = 100 mA IOL = 4 mA VOL IOL = 8 mA IOL = 16 mA IOL = 24 mA IOL = 32 mA II Ioff ICC ICC VI = 5.5 V or GND VI or VO = 5.5 V VI = 5.5 V or GND, One input at VCC - 0.6 V, IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 1.65 V to 5.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 5.5 V 1.65 V 2.3 V 3V 4.5 V 0 to 5.5 V 0 1.65 V to 5.5 V 3 V to 5.5 V 3.3 V 3.5 MIN VCC - 0.1 1.2 1.9 2.4 2.3 3.8 0.1 0.45 0.3 0.4 0.55 0.55 1 10 10 500 mA mA mA mA pF V V TYP MAX UNIT
Ci VI = VCC or GND All typical values are at VCC = 3.3 V, TA = 25C.
switching characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd FROM (INPUT) A TO (OUTPUT) Y VCC = 1.8 V 0.15 V MIN 2 MAX 9.9 VCC = 2.5 V 0.2 V MIN 1.5 MAX 6 VCC = 3.3 V 0.3 V MIN 1 MAX 3.5 VCC = 5 V 0.5 V MIN 1 MAX 2.9 ns UNIT
switching characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
PARAMETER tpd FROM (INPUT) A TO (OUTPUT) Y VCC = 1.8 V 0.15 V MIN 3.2 MAX 8.6 VCC = 2.5 V 0.2 V MIN 1.5 MAX 4.4 VCC = 3.3 V 0.3 V MIN 1.5 MAX 4.1 VCC = 5 V 0.5 V MIN 1 MAX 3.2 ns UNIT
operating characteristics, TA = 25C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V TYP 16 VCC = 2.5 V TYP 16 VCC = 3.3 V TYP 16 VCC = 5 V TYP 18 UNIT pF
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SN74LVC1G34 SINGLE BUFFER GATE
SCES519A - DECEMBER 2003 - REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION
S1 VLOAD Open GND RL TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open VLOAD GND
From Output Under Test CL (see Note A)
RL
LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI VCC VCC 3V VCC tr/tf 2 ns 2 ns 2.5 ns 2.5 ns VM VCC/2 VCC/2 1.5 V VCC/2 VLOAD 2 x VCC 2 x VCC 6V 2 x VCC CL 15 pF 15 pF 15 pF 15 pF RL 1 M 1 M 1 M 1 M V 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input tw VI Input VM VM 0V VOLTAGE WAVEFORMS PULSE DURATION VI Input tPLH Output tPHL VM VM VM VM 0V tPHL VOH VM VOL tPLH VOH Output VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) Output Control tPZL VM tPZH VM VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM VM 0V tPLZ VLOAD/2 VOL + V tPHZ VOH - V VOH 0 V VOL Data Input tsu VM th VI VM 0V VM 0V
Output Waveform 1 S1 at VLOAD (see Note B)
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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SN74LVC1G34 SINGLE BUFFER GATE
SCES519A - DECEMBER 2003 - REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION
S1 VLOAD Open GND RL TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open VLOAD GND
From Output Under Test CL (see Note A)
RL
LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI VCC VCC 3V VCC tr/tf 2 ns 2 ns 2.5 ns 2.5 ns VM VCC/2 VCC/2 1.5 V VCC/2 VLOAD 2 x VCC 2 x VCC 6V 2 x VCC CL 30 pF 30 pF 50 pF 50 pF RL 1 k 500 500 500 V 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input tw VI Input VM VM 0V VOLTAGE WAVEFORMS PULSE DURATION VI Input tPLH Output tPHL VM VM VM VM 0V tPHL VOH VM VOL tPLH VOH Output VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) Output Control tPZL VM tPZH VM VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM VM 0V tPLZ VLOAD/2 VOL + V tPHZ VOH - V VOH 0 V VOL Data Input tsu VM th VI VM 0V VM 0V
Output Waveform 1 S1 at VLOAD (see Note B)
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device SN74LVC1G34DBVR SN74LVC1G34DBVT SN74LVC1G34DCKR SN74LVC1G34DCKT SN74LVC1G34YEPR SN74LVC1G34YZPR
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SOT-23 SOT-23 SC70 SC70 WCSP WCSP
Package Drawing DBV DBV DCK DCK YEP YZP
Pins Package Eco Plan (2) Qty 5 5 5 5 5 5 3000 250 3000 250 3000 3000 Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) None Pb-Free (RoHS)
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU SNPB SNAGCU
MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS025C - FEBRUARY 1997 - REVISED FEBRUARY 2002
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE PACKAGE
0,65 5 4
0,30 0,15
0,10 M
1,40 1,10
2,40 1,80
0,13 NOM
1 2,15 1,85
3
Gage Plane
0,15 0-8 0,46 0,26
Seating Plane 1,10 0,80 0,10 0,00 0,10
4093553-2/D 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-203
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